1. Field of the Invention
This invention relates to a buffer circuit which can be used for the input stage of a semiconductor integrated circuit device, for example, and more particularly to a complementary buffer circuit having two buffer circuits connected in a complementary configuration.
2. Description of the Related Art
Generally, a buffer circuit is connected in the input stage of a semiconductor integrated circuit device. Various types of buffer circuits are known, and a differential amplification type buffer circuit may be used in a CMOS semiconductor integrated circuit device. This type of buffer circuit is used to convert an input signal of TTL (transistor transistor logic) level into a signal of CMOS logic level and supplies the converted signal to the internal circuit of the device. The differential amplification type buffer circuit includes a pair of driving MOS transistors and a current mirror circuit acting as the load of the MOS transistors. An input signal is supplied to the gate of one of the MOS transistors and a reference voltage is applied to the gate of the other MOS transistor. There are two types of buffer circuits, one type including a P-channel driving MOS transistor and a current mirror circuit formed of N-channel MOS transistors and the other type including an N-channel driving MOS transistor and a current mirror circuit formed of P-channel MOS transistors.
However, in the former type buffer circuit, the transition of an output signal from the high level to the low level tends to be delayed when the power source voltage is lowered by noise or the like. In contrast, in the latter type buffer circuit, the transition of an output signal from the low level to the high level tends to be delayed when the ground potential rises by noise or the reference potential is lowered.
As described above, when the rise or fall of an output signal of the buffer circuit is delayed and if a desired output level cannot be stably obtained, then the internal circuit of the device may be erroneously operated.